Complementary metal oxide semiconductor (CMOS) circuits of present semiconductor technology comprise n-type field effect transistors (nFETs), which utilize electron carriers for their operation, and p-type field effect transistors (pFETs), which utilize hole carriers for their operation. CMOS circuits are typically fabricated on Si wafers having a single crystal orientation, ordinarily (100). However, since electrons have a higher mobility in Si with a (100) surface orientation (vs. a (110) orientation) and holes have higher mobility in Si with a (110) surface orientation (vs. a (100) orientation), there is great interest in fabricating CMOS circuits on hybrid orientation substrates so that nFETs may be formed in (100)-oriented Si and pFETs may be formed in (110)-oriented Si.
Examples of some prior art hybrid orientation substrates are shown in FIGS. 1A-1G. All the illustrated prior art substrates comprise coplanar, or substantially coplanar, surface regions of differently oriented single-crystal semiconductors, denoted as 10 and 20, separated by insulator-filled isolation trenches 30. (Here and in the figures that follow, different direction of crosshatching is used to indicate different semiconductor orientations.) Base substrate 40 is a single-crystal semiconductor having the same orientation as the semiconductor region 20. Base substrate 50 is typically a semiconductor or an insulator, orientation unspecified. Single-crystal semiconductor regions 60, 70, and 80 have an orientation that is the same as the orientation as the semiconductor region 20. Semiconductor regions 10 and 20 comprise part of a bulk substrate for the structures of FIGS. 1A and 1F; part of a semiconductor-on-insulator (SOI) substrate for the structures of FIGS. 1C, 1D, 1E, and 1G, with buried insulator layers 90 and/or localized buried insulator layers 100; and part of a mixed bulk/SOI substrate for the structure of FIG. 1B, with localized buried insulator layer 110. The structure of FIG. 1D has a layer of insulator between the semiconductor region 10 and the underlying semiconductor region 70, whereas the structures of FIGS. 1C and 1G have a direct semiconductor-to-semiconductor bonded (DSB) interface between the semiconductor region 10 and the underlying semiconductor regions 60 and 80.
Fabrication methods for the substrates shown in FIGS. 1A-1G vary, but all typically start with a (jkl)-oriented semiconductor layer bonded to a (j′k′l′)-oriented semiconductor handle wafer or handle wafer layer. Depending on the fabrication method, the bonding may be direct (e.g., resulting in a semiconductor-to-semiconductor interface) or indirect (e.g., bonding in which an oxide or other insulating layer remains at the bonded interface in at least some areas). To produce the substrate structures of FIGS. 1A-1E, selected regions of the (jkl)-oriented semiconductor layer are replaced (along with any exposed buried insulator regions, if desired) with a semiconductor having the (j′k′l′) orientation of the substrate. This may be done, for example, by a trench/epitaxial-growth process (such as described, for example, in U.S. Pat. No. 7,329,923, the contents of which were previously incorporated herein by reference) in which the (jkl)-oriented semiconductor is first etched away in selected regions to form openings that expose the underlying (j′k′l′)-oriented semiconductor and then replaced by an epitaxially-grown semiconductor having the orientation of the substrate. Alternatively, one may use an amorphization/templated recrystallization (ATR) process (such as described, for example, in U.S. patent application Ser. No. 10/725,850, which disclosure was also previously incorporated herein by reference) in which selected regions of the (jkl)-oriented semiconductor are first amorphized to a depth below a DSB interface and then epitaxially recrystallized using the underlying (j′k′l′)-oriented semiconductor as a template. Additional process steps may be performed to introduce or enhance buried insulator layers 90, 100, and 110, as described, for example, in U.S. patent application Ser. No. 10/725,850 and U.S. Pat. No. 7,253,034, the contents of which were also incorporated herein by reference. The structures of FIGS. 1F-1G would typically be fabricated by an in-place bonding technique (such as described, for example, in U.S. Pat. No. 7,238,589, the contents of which were also incorporated herein by reference), or by simply etching away regions of a (jkl)-oriented semiconductor layer directly bonded to a (j′k′l′)-oriented substrate layer.
To date, all the nFETs and pFETs in CMOS circuits fabricated in such hybrid orientation substrates have one feature in common: the channel and source/drain regions of each FET are formed in a semiconductor having a single orientation, one selected to optimize the mobility for that FET's carriers. An example of such a conventional FET is shown in FIG. 2, where FET 200, formed in single-orientation semiconductor 210, comprises source and drain regions 220 bordered by insulator-filled isolation trenches 30, source/drain extensions 230, a semiconductor channel region (within region 240), gate dielectric 250, and conductive gate 260. (For clarity, the source/drain regions and source/drain extensions in subsequent figures may be identified by labels associated with their boundaries even though it is the semiconductor material within these boundaries that constitute the actual source/drains and source/drain extensions.) Other common and/or advantageous FET components such as well implant regions, halo implants, sidewall spacers on the gate, raised source/drains, gate contacts, source/drain contacts, overlayers and/or replacement source/drain regions producing channel stress, etc., may be present, but are not shown in FIG. 2.
FETs with the geometry of FIG. 2 present no problem for hybrid orientation substrates having the structures of FIGS. 1B, 1D, or 1E, in which the single-crystal semiconductors 10 and 20 are bounded below by a bulk semiconductor of the same orientation (for the case of semiconductor 20) or by an underlying layer of insulator (for the case of semiconductor 20). However, such FET geometries are less compatible with hybrid orientation substrates having the structures of FIGS. 1A, 1C, 1F, and 1G, where (jkl)-oriented regions 10 are bounded below by (j′k′l′)-oriented regions 60, 70, or 80, because the FET must either be “thin” (i.e., the source/drain regions must be shallower than the bonded (jkl)-oriented semiconductor layer) or, equivalently, disposed in a (jkl)-oriented DSB layer that is thicker than the depth of the source/drain regions. Such restrictions can be quite limiting: many CMOS circuits in bulk semiconductors utilize FETs with deep source/drains, and hybrid orientation substrates are typically easier to form when the DSB layer is thin. Thinner DSB layers are particularly desirable for hybrid substrates fabricated by ATR techniques, since the defectivity of the recrystallized semiconductor material tends to increase with the amorphization depth (which is constrained to be greater than the thickness of the DSB layer). For example, N. Burbure and K. S. Jones (Mat. Res. Soc. Symp. Proc. 810 C4.19.1, 2004) show that the lateral dimensions of corner defects left after ATR on Si substrates patterned with oxide-filled trenches are directly proportional to the depth of the amorphizing implant.
It would therefore be desirable to have an FET structure that has the advantages and performance of an FET fabricated in the optimum orientation of a semiconductor without requiring the entirety of the FET (i.e., its source/drain and channel) to be fabricated in a semiconductor with the optimum orientation.